The present disclosure relates to a delta-sigma A/D converter, a limiter circuit used for the same and a television receiver using the delta-sigma A/D converter.
As is well known, the present television broadcasting in our country is digital broadcasting. Television receivers are employing digital demodulation circuits attaining demodulation for high quality signals from the digital broadcasting.
FIG. 10 is a block diagram of a television receiver according to an existing technology.
A high frequency signal according to a radio wave received by an antenna 102 is amplified by a high frequency amplifier (hereinafter abbreviated as “RF amplifier”) 103, and after that, inputted to two mixers.
To the first mixer 104, a local oscillation signal is inputted from a PLL (Phase Locked Loop) 105 which is a known local oscillator, and an I-channel signal as an intermediate frequency signal (hereinafter abbreviated as “IF”) is outputted therefrom.
To the second mixer 106, a local oscillation signal obtained by 90-degree phase shift on the local oscillation signal of the PLL 105 by a 90-degree phase shifter 107 is inputted, and a Q-channel signal as an IF is outputted therefrom.
The I-channel signal and Q-channel signal are inputted to a polyphase filter 1002 and their noise components are removed therefrom. After that, they are converted into digital signals by a Nyquist A/D converter 1003 and inputted to a demodulator 1004. The demodulator 1004 performs demodulation to obtain a video signal and a voice signal from the digital signals and supplies the video signal and voice signal to a display 114 and a loud speaker 115, respectively.
In addition, Japanese Patent Laid-Open No. 2010-263483 (hereinafter referred to as Patent Literature 1) is a document disclosing a technology seeming to be similar to the present disclosure.